High speed input/output (I/O) busses cause considerable power to be consumed by I/O buffers in dynamic random access memory (DRAM) chips. Lower power complimentary metal oxide semiconductor (CMOS) busses have not supported the high edge rates used at higher frequencies, such as 400 MHz or 800 MHz data rates currently in use. Such busses have been modified such that they no longer switch rail to rail, causing an increase in current drain, and hence heat generation. Thevenin terminations on the I/O bus have been used to maintain fast edge rates. Such terminations reference the bus output to a low impedance, but cause excess power draw when lower performance is expected from the bus and memory chip.
Prior methods of power reduction have been suggested for thermal control in memory devices. One simple method involves lowering the speed of the synchronous or clocked bus. This method does relieve thermal stress by lowering the power consumption rate of the system, but it only acts to delay the overall power consumption by delaying fetches from the memory device.
Another prior method involves momentarily disabling the memory device itself. This is referred to as bandwidth throttling, and acts to periodically disable the memory device in response to either sensed or perceived high temperatures. Bandwidth throttling has also been used in response to an activity detector detecting too much traffic on the bus. Bandwidth throttling reduces potential performance obtained from the memory device.